FPGA Design Engineer
Location :
Norwalk CT US 06850
Job Type :
Temp/Contract
Reference Code :
20292-BZ1
Compensation : open - 60-80/h
Start Date :
09/01/2020
Hours :
Full Time
Required Years of Experience :
5
Required Education :
BS Electrical Engineering
Travel :
No
Relocation :
No
Job Industry :
Engineering
Job Description :
- Contract position for an FPGA Design Engineer to provide FPGA designs supporting electronic and electrical designs for the entire development process.
- Conceptional design through detail design, prototypes through volume manufacture, initial integration through qualification.
- Collaborate with a multidiscipline project team, perform engineering analysis and generate detailed design documents.
- Determine architecture, system verification and detailed design approach.
- Define module interfaces and all aspects of device design and simulation coordinated with the PC Board Designers.
- Evaluate the process flow including but not limited to high level design, synthesis, place and route, timing constraints and power utilization.
- Develop test, simulation plans and design verification test plans at design top level.
- Develop, implement and supervise design verification test plans at system level.
- Support the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the FPGA development life cycle.
- May provide leadership and/or direction to lower level employees.
- Independently determine approach to solutions and get alignment from System Engineers and board developers.
- Contribute to design and development of FPGA hardware for control, communications systems and digital signal processing (DSP) platforms.
Required Qualifications :
- BS Electrical Engineering, MS degree preferred/
- Minimum 5 years experience with FPGA design, verification and validation.
- Experience with FPGA engineering concepts, principles, and theories.
- Experience with FPGA design languages and tools including VHDL and UVM or OSVVM.
- Altera High Level Synthesis is preferred.
- Experience with Modelsim, Quartus, Mentor CDC a plus
- Experience with FPGA SoC, including Avalon and AXI architectures.
- Experience with architecting and implementing embedded processors including NIOS.
- Experience implementing IP blocks based on interface requirements and designing the required interface logic to overall FPGA architecture.
- Expertise using VHDL for implementation and verification of FPGA designs.
Contact: Bill Zukowsky
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